In making electronic packages that use lead frames, there are several process steps that subject the lead frames to mechanical and thermal stresses. The finer geometries of current lead frames and the ever-increasing integration of circuits on semiconductor chips have resulted in processing that places even greater stress on the lead frames. Finely configured lead frames often resemble very delicate embroidery, or stencil-like metal structures that tend to bend, break, disfigure and deform easily, (See FIGS. 1a and 1b). Such conventional lead frames are used in the industry to create a variety of chip packages, including wire bonded and flip-chip (FC) packages, (See FIGS. 2a-2d and 3a-3b).
Conventional lead frames generally lack structural rigidity. The finger-like portions of lead frames can be quite flimsy and difficult to hold in position. This leads to handling flaws, damage and distortion in assembly processes and complicated wire bonding situations. Consequently, bond parameters have to be optimized to compensate for lead frame bouncing during the bonding process. A failure to optimize the bonding parameters to compensate for the mechanical instability of the lead frame can result in poor bond adhesion, and hence poor quality and poor reliability of the bond.
The large metal plate portions of a typical lead frame extend from a central portion, known as the chip receiving area, also known as a chip-pad. The chip is usually attached to the receiving area with the backside down, and the front side is positioned face up with terminals located peripherally on the perimeter of the chip, or over the surface of the chip in the form of an array. The receiving area typically has dimensions of about 5 mm×5 mm, and the leads extending outwardly from the chip-pad area have typical dimensions of about 10 min long×1 mm wide×0.2 mm thick. The lead frame is typically held down by a vacuum chuck and mechanical clamps. The chuck and clamps must be refitted for lead frames of different sizes and shapes. The present invention alleviates this problem.
The prior art has not shown any lead frames that can withstand the stresses encountered in current semiconductor packaging processes and that can be manufactured in a cost effective manner. The present invention achieves this objective by providing a partially patterned lead frame that not only improves the manufacturability of the lead frame itself, but also improves the integrity and reliability of the electronic packages that are formed therefrom. The present invention also addresses a continued need for increased device complexity, such as high I/O counts, multi-chip design, system in package, and flexibility on routing, that conventional lead frames are unable to offer.
Computer chips are also continuously shrinking in size. For a lead frame having particular dimensions, the use of increasingly smaller sized chips causes the wire bonds between the chip terminals and electrical lands to become longer. The need for longer wires can cause wire sway during processing and can potentially make certain types of chip scale packages prone to wire shorting.
Increasing wire length also affects unit cost. Typically, gold wires are used to connect the computer chip to the lands. The price of gold has virtually tripled in the last five years, and as the chip size decreases, the amount of gold wire increases, causing significant pricing pressure on chip package manufacturers. Although coated wires are an alternative to gold wires, they are 2-3 times more expensive.
The placement of the leads on the lead frame can sometimes be adjusted, but the ability to modify placement of leads is dependent upon the configuration of the lead frame and by the manufacturer's production capability. A fixed lead position can potentially require special looping techniques when bonding wires, slowing down the bonding process without completely eliminating the possibility of wire shorting.
Some computer packages require radio frequency shielding (RF shielding) to prevent electromagnetic fields from interfering with proper functioning of the package while in operation. Laminated devices commonly have such RF shielding, but it is a very costly feature. There are industry-accepted electronics standards (“moisture sensitivity levels”) for the amount of time that a moisture sensitive device can be exposed to ambient room conditions. Many laminates are rated for MSL 3. At MSL 3, components must be mounted and reflowed within 168 hours after removal from a moisture-barrier bag.
Sawing is commonly used to singulate the lead frames to form individual chip scale packages, and to partially cut into the lead frames to expose the intended metal layer for connection to particular features, such as EMI (electromagnetic interference) shielding coatings. However, multiple passes with a saw can affect productivity and production yield. As exposed metal surfaces are typically 5-18 μm thick, a high level of control of the sawing process is important to ensure proper blade height.